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| PRELIMINARY DATA SHEET SD1200 Analog-Interface XGA/SXGA TFT LCD Display Controller September 1998 SmartASIC, Inc. SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET SD1200 PRELIMINARY DATA SHEET PRSD-1200-A September 1998 Document PRSD-1200-A Revisions First Preliminary Datasheet Date September 1998 Copyright 1998, SmartASIC, Inc. All Right Reserved SmartASIC, Inc. reserves the right to change or modify the information contained herein without notice. It is the customer's responsibility to ensure he/she has the most recent revision of the user guide. SmartASIC, Inc. makes no warranty for the use of its products and bears no responsibility for any error or omissions, which may appear in this document. September, 1998 SmartASIC Confidential 2 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET SD1200 Analog-Interface XGA/SXGA TFT LCD Display Controller Features * * * * * * * Highly integrated analog interface XGA/SXGA TFT LCD Display Controller Handle both 24-bit and 48-bit sampled RGB input up to SXGA (1280x1024) @ 85Hz Support various PC graphics cards Drive 48-bit digital RGB output up to SXGA (1280x1024) @ 75Hz Support various TFT LCD panels Truly "Plug and Display" no special driver running on PC Implement proprietary SmartDisplay technology for - input mode detection and auto calibration - output image scaling and interpolation - 16.7 million true color support for 6 bit panel - robust detection and handling of invalid input modes Advanced input mode detection and auto calibration - input refresh rate detection - input format detection - input sync polarity detection - image expansion - input frequency detection - optimal sampling clock phase calibration Advanced image scaling and interpolation with - automatic image centering - automatic image expansion in both horizontal and vertical directions programmable horizontal and vertical expansion ratio - programmable horizontal and vertical interpolation algorithm True color support for 6 bit panel - Proprietary dithering based on both intensity and spatial information - Optional frame modulation Robust handling of invalid input conditions - detect no input signal - detect input signal beyond specified acceptable range - output status indicators - generate output signal even when no input signal Support multiple TFT LCD panels - programmable output timing parameters to match specifications of various TFT LCD panels - support power On/Off sequence - Output signal is synchronized with the input signal with the same frame rate Low-cost system solution - no external frame buffer required - 2-wire I2C serial interface for EEPROM and CPU - programmable OSD mixer - direct interface to external ADC's and PLL's - 160 pin PQFP Package - 5.0V and 3.3V supply * * * * * * September, 1998 SmartASIC Confidential 3 1. OVERVIEW The SD1200 is an IC designed for analog-interface XGA/SXGA TFT LCD monitors. An analog-interface LCD monitor takes analog RGB signals from a graphic card of a personal computer, the exact same input interface as a conventional CRT monitor. This feature makes analog-interface LCD monitor a true replacement of a conventional CRT monitor. The analog input RGB signals are first sampled by six channels of 8-bit A/D converters, and the 48-bit RGB data are then fed into the SD1200. The SD1200 is capable of performing automatic detection of the display resolution and timing of input signals generated from various PC graphic cards. No special driver is required for the timing detection, nor does any manual adjustment. The SD1200 then automatically scales the input image to fill the full screen of the LCD monitor. The SD1200 can interface with TFT LCD panels from various manufacturers by generating 48-bit RGB signal to the LCD panel based upon the timing parameters saved in the EEPROM. The SD1200 provides two distinguished features to the TFT LCD monitor solution. The first one is "plug-and-play", and the second one is "cost-effective system solution". To be truly plug-and-display, the SD1200 performs automatic input mode detection and auto phase calibration, so that the LCD monitor can ensure the A/D converters' sample clock to be precisely synchronized with the input video data, and to preserve the highest image bandwidth for the highest image quality. Furthermore, the SD1200 can generate output video even when the input signal is beyond the specifications, or no input signal is fed. For "cost-effective system solution", the SD1200 implements many system support features such as OSD mixer, error status indicators, 2-wire I2C serial interface for both EEPROM and host CPU interface, and low-cost IC package. Another important contributing factor is that SD1200 does not require external frame buffer memory for the automatic image scaling and synchronization. The SD1200 can handle input signal up to SXGA (1280x1024) resolution at 75Hz refresh rate, and produce output signal at SXGA resolution at 75Hz refresh rate (subject to the limitation of LCD panel). SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET Figure 1 shows the block diagram of the SD1200 as well as the connections of important system components around the SD1200. Figure 1: SD1200 Functional Block Diagram ADC Phase Control Input mode Detection & Auto Calibration Buffer Memory Scaling Interpolation Dithering Write Control Read Control OSD Mixer TFT LCD Monitor Input PLL CPU Interface E2ROM Interface CPU Output PLL E2PROM September, 1998 SmartASIC Confidential 5 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 2. PIN DESCRIPTION Figure 2: SD1200 package diagram 120 81 12 80 SmartASIC SD1200 160 41 1 40 September, 1998 SmartASIC Confidential 6 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET able 1: SD1200 pin description (sorted by pin number) Symbol B_IN06 B_IN07 B_IN10 B_IN11 B_IN12 B_IN13 DATA_SEL B_IN14 B_IN15 B_IN16 B_IN17 GND HSYNC_I VSYNC_I MODE_IN0 PIN Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Voltage 5 5 5 5 5 5 5 5 5 5 5 5 5 5 I/O I I I I I I I I I I I Description Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Select Input Odd/Even Data Input Color Blue Input Color Blue Input Color Blue Input Color Blue Ground I Input HSYNC (active LOW) I Input VSYNC (active LOW) I Input Mode Select 1: double 24 bit RGB 0: single 24 bit RGB I Device ID bit 4 for CPU Interface (Pull High Internally) +5V Power Supply I Device ID bit 5 for CPU Interface (Pull High Internally) I Device ID bit 6 for CPU Interface (Pull High Internally) O SCL in I2C for EEPROM interface I/O SDA in I2C for EEPROM interface Ground I SCL in I2C for CPU interface I/O SDA in I2C for CPU interface O PWM control signal (Detail description in PWM Operation Section) I Free Running Clock (default: 1MHz) +5V Power Supply O Feedback of free Running Clock I System Reset ( active LOW) I OSD Color Red I OSD Color Green I OSD Color Blue I OSD Mixer Enable =0, No OSD output =1,R_OUT[7:0]= {R_OSD repeat 8 times} G_OUT[7:0]= {G_OSD repeat 8 times } B_OUT[7:0]= {B_OSD repeat 8 times } 1 Manufacturing test pin (NC) I Manufacturing test pin (NC) I Manufacturing test pin (NC) O Manufacturing test pin (NC) O Manufacturing test pin (NC) O Default HSYNC generated by ASIC (active MODE_IN1 VDD_5V MODE_IN2 MODE_IN3 ROM_SCL ROM_SDA GND CPU_SCL CPU_SDA PWM_CTL CLK_1M VDD_5V CLK_1M_O RESET_B R_OSD G_OSD B_OSD EN_OSD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SCAN_EN TEST_EN TEST_H TST_DONE FAIL_H HSYNC_X 34 35 36 37 38 39 5 5 5 5 5 5 September, 1998 SmartASIC Confidential 7 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET LOW) Default VSYNC generated by ASIC (active LOW) Ground Input PLL Feedback Clock Input PLL Output Clock Output PLL Feedback Clock Output PLL Output Clock Output HSYNC Output VSYNC Output Clock to Control Panel Output Display Enable for Panel (active HIGH) +5V Power Supply Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel +3.3V Power Supply Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Ground Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel +5V Power Supply Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Ground Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel +3.3V Power Supply Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Ground Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel +5V Power Supply Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel VSYNC_X GND FCLK0 VCLK0 FCLK1 VCLK1 HSYNC_O VSYNC_O DCLK_OUT DE_OUT VDD_5V R_OUT0_E R_OUT1_E R_OUT2_E R_OUT3_E VDD_3.3V R_OUT4_E R_OUT5_E R_OUT6_E R_OUT7_E GND R_OUT0_O R_OUT1_O R_OUT2_O R_OUT3_O VDD_5V R_OUT4_O R_OUT5_O R_OUT6_O R_OUT7_O GND G_OUT0_E G_OUT1_E G_OUT2_E G_OUT3_E G_OUT4_E VDD_3.3V G_OUT5_E G_OUT6_E G_OUT7_E GND G_OUT0_O G_OUT1_O G_OUT2_O G_OUT3_O VDD_5V G_OUT4_O G_OUT5_O G_OUT6_O G_OUT7_O 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 5 O 5 5 5 5 3.3 3.3 3.3 3.3 5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 3.3 3.3 3.3 3.3 O I O I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O September, 1998 SmartASIC Confidential 8 SmartASIC, Inc. SD1200 GND B_OUT0_E B_OUT1_E B_OUT2_E B_OUT3_E B_OUT4_E B_OUT5_E B_OUT6_E VDD_3.3V B_OUT7_E GND B_OUT0_O B_OUT1_O B_OUT2_O B_OUT3_O VDD_5V B_OUT4_O B_OUT5_O B_OUT6_O B_OUT7_O GND R_IN00 R_IN01 R_IN02 R_IN03 VDD_5V R_IN04 R_IN05 R_IN06 R_IN07 GND R_IN10 R_IN11 R_IN12 R_IN13 VDD_5V R_IN14 R_IN15 R_IN16 R_IN17 GND G_IN00 G_IN01 G_IN02 G_IN03 VDD_5V G_IN04 G_IN05 ADC_CLK0 G_IN06 G_IN07 GND 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 PRELIMINARY DATA SHEET Ground Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel +3.3V Power Supply Output Color Blue Even Pixel Ground Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel +5V Power Supply Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Ground Input Color Red Input Color Red Input Color Red Input Color Red +5V Power Supply Input Color Red Input Color Red Input Color Red Input Color Red Ground Input Color Red Input Color Red Input Color Red Input Color Red +5V Power Supply Input Color Red Input Color Red Input Color Red Input Color Red Ground Input Color Green Input Color Green Input Color Green Input Color Green +5V Power Supply Input Color Green Input Color Green Sample Clock for ADC 0 Input Color Green Input Color Green Ground 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 3.3 3.3 3.3 3.3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I I I I I I I O I I September, 1998 SmartASIC Confidential 9 SmartASIC, Inc. SD1200 G_IN10 G_IN11 ADC_CLK1 G_IN12 G_IN13 VDD_5V G_IN14 G_IN15 G_IN16 G_IN17 GND B_IN00 B_IN01 B_IN02 B_IN03 VDD_5V B_IN04 B_IN05 GND 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 I I O I I I I I I I I I I I I PRELIMINARY DATA SHEET Input Color Green Input Color Green Sample Clock for ADC 1 Input Color Green Input Color Green +5V Power Supply Input Color Green Input Color Green Input Color Green Input Color Green Ground Input Color Blue Input Color Blue Input Color Blue Input Color Blue +5V Power Supply Input Color Blue Input Color Blue Ground September, 1998 SmartASIC Confidential 10 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET Table 2: SD1200 pin description (sorted by function) Symbol R_IN00 R_IN01 R_IN02 R_IN03 R_IN04 R_IN05 R_IN06 R_IN07 R_IN10 R_IN11 R_IN12 R_IN13 R_IN14 R_IN15 R_IN16 R_IN17 G_IN00 G_IN01 G_IN02 G_IN03 G_IN04 G_IN05 G_IN06 G_IN07 G_IN10 G_IN11 G_IN12 G_IN13 G_IN14 G_IN15 G_IN16 G_IN17 B_IN00 B_IN01 B_IN02 B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 B_IN10 B_IN11 B_IN12 B_IN13 B_IN14 B_IN15 B_IN16 B_IN17 PIN Number 111 112 113 114 116 117 118 119 121 122 123 124 126 127 128 129 131 132 133 134 136 137 139 140 142 143 145 146 148 149 150 151 153 154 155 156 158 159 1 2 3 4 5 6 8 9 10 11 Voltage 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 I/O I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Description Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Red Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Green Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue Input Color Blue September, 1998 SmartASIC Confidential 11 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET HSYNC_I VSYNC_I MODE_IN0 13 14 15 5 5 5 I I I MODE_IN1 MODE_IN2 MODE_IN3 ADC_CLK0 ADC_CLK1 16 18 19 138 144 5 5 5 5 5 I I I O O Input HSYNC (active LOW) Input VSYNC (active LOW) Input Mode Select 1: double 24 bit RGB 0: single 24 bit RGB Device ID bit 4 for CPU Interface (Pull High Internally) Device ID bit 5 for CPU Interface (Pull High Internally) Device ID bit 6 for CPU Interface (Pull High Internally) Sample Clock for ADC 0 Sample Clock for ADC 1 R_OUT0_E R_OUT1_E R_OUT2_E R_OUT3_E R_OUT4_E R_OUT5_E R_OUT6_E R_OUT7_E R_OUT0_O R_OUT1_O R_OUT2_O R_OUT3_O R_OUT4_O R_OUT5_O R_OUT6_O R_OUT7_O G_OUT0_E G_OUT1_E G_OUT2_E G_OUT3_E G_OUT4_E G_OUT5_E G_OUT6_E G_OUT7_E G_OUT0_O G_OUT1_O G_OUT2_O G_OUT3_O G_OUT4_O G_OUT5_O G_OUT6_O G_OUT7_O B_OUT0_E B_OUT1_E B_OUT2_E 51 52 53 54 56 57 58 59 61 62 63 64 66 67 68 69 71 72 73 74 75 77 78 79 81 82 83 84 86 87 88 89 91 92 93 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Even Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Red Odd Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Even Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Green Odd Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel September, 1998 SmartASIC Confidential 12 SmartASIC, Inc. SD1200 B_OUT3_E B_OUT4_E B_OUT5_E B_OUT6_E B_OUT7_E B_OUT0_O B_OUT1_O B_OUT2_O B_OUT3_O B_OUT4_O B_OUT5_O B_OUT6_O B_OUT7_O HSYNC_O VSYNC_O DCLK_OUT DE_OUT 94 95 96 97 99 101 102 103 104 106 107 108 109 46 47 48 49 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 O O O O O O O O O O O O O O O O O PRELIMINARY DATA SHEET Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Even Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output Color Blue Odd Pixel Output HSYNC Output VSYNC Output Clock to Control Panel Output Display Enable for Panel (active HIGH) Input PLL Feedback Clock Input PLL Output Clock Output PLL Feedback Clock Output PLL Output Clock FCLK0 VCLK0 FCLK1 VCLK1 ROM_SCL ROM_SDA CPU_SCL CPU_SDA PWM_CTL CLK_1M CLK_1M_O RESET_B HSYNC_X VSYNC_X 42 43 44 45 20 21 23 24 25 26 28 29 39 40 5 5 5 5 5 5 5 5 5 5 5 5 5 5 O I O I O SCL in I2C for EEPROM interface I/O SDA in I2C for EEPROM interface I SCL in I2C for CPU interface I/O SDA in I2C for CPU interface O I O I O O PWM control signal (Detail description in PWM Operation Section) Free Running Clock (default: 1MHz) Feedback of free Running Clock System Reset ( active LOW) Default HSYNC generated by ASIC (active LOW) Default VSYNC generated by ASIC (active LOW) OSD Color Red OSD Color Green OSD Color Blue OSD Mixer Enable =0, No OSD output =1,R_OUT[7:0]= {R_OSD repeat 8 times} G_OUT[7:0]= {G_OSD repeat 8 times } B_OUT[7:0]= {B_OSD repeat 8 times } Manufacturing test pin (NC) Manufacturing test pin (NC) R_OSD G_OSD B_OSD EN_OSD 30 31 32 33 5 5 5 5 I I I I SCAN_EN TEST_H 34 36 5 5 1 I September, 1998 SmartASIC Confidential 13 SmartASIC, Inc. SD1200 FAIL_H TST_DONE TEST_EN DATA_SEL VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V VDD_5V 38 37 35 7 17 27 50 65 85 105 115 125 135 147 157 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 O O I I PRELIMINARY DATA SHEET Manufacturing test pin (NC) Manufacturing test pin (NC) Manufacturing test pin (NC) Select Input Odd/Even Data +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply +5V Power Supply VDD_3.3V VDD_3.3V VDD_3.3V GND GND GND GND GND GND GND GND GND GND GND GND GND GND 55 76 98 12 22 41 60 70 80 90 100 110 120 130 141 152 160 3.3 3.3 3.3 +3.3V Power Supply +3.3V Power Supply +3.3V Power Supply Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground September, 1998 SmartASIC Confidential 14 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 3. FUNCTIONAL DESCRIPTION The SD1200 has the following major function blocks: 1. Input mode detection & auto calibration block 2. Buffer memory and read/write control block 3. Image scaling, interpolation and dithering block 4. OSD mixer and LCD interface block 5. EEPROM interface block 6. CPU interface block The following sections will describe the functionality of these blocks. 3.1. 3.1.1. Input mode detection & auto calibration block Supported input modes The SD1200 accepts seven different input video modes: * * * * * * * 640 x 350 640 x 400 720 x 400 640 x 480 (VGA) 800 x 600 (SVGA) 1024 x 768 (XGA) 1280 x 1024 (SXGA) There is no frame rate restriction on the input modes. However, since the output signal is synchronized with the input signal at the same refresh rate. The input refresh rate has to be within the acceptable range of the LCD panel. 3.1.2. Input mode detection The SD1200 can automatically detect the mode of the input signal without any user adjustment or driver running on the PC host or external CPU. This block September, 1998 SmartASIC Confidential 15 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET automatically detects polarity of input synchronization and the sizes of back porch, valid data window and the synchronization pulse width in both vertical and horizontal directions. The size information is then used not only to decide the input resolution, to generate the frequency divider for the input PLL, to lock the PLL output clock with HSYNC, but also to automatically scale the image to full screen, and to synchronize the output signal with the input signal. The detection logic is always active to automatically detect any changes to the input mode. Users can manually change the input mode information at run time through the CPU interface. Detail operation of the CPU interface is described in Section. "CPU Interface". 3.1.3. Auto calibration The SD1200 can automatically calibrate the phase of the sample clock in order to preserve the bandwidth of input signal and get the best quality. The SD1200 implements a proprietary image quality function. During auto-calibration process, the SD1200 continues search for the best phase to optimize the image quality. The output image may display some jitter and blurring during the auto-calibration process, and the image will become crisp and sharp once the optimum phase is found. User can change the sampling clock phase value by the external CPU. Detail operation of the CPU interface is described in Section. "CPU Interface". The auto calibration process can be delayed and even disabled by the external CPU if system designer wants to have his/her own implementation. 3.1.4. PWM operation The SD1200 implements a very unique algorithm to adjust the phase of the A/D converter's sampling clock. An external delay circuitry is required to compliment the SD1200 for the auto-calibration process. The SD1200 generates a Pulse-Width Modulated (PWM) signal to the external delay circuitry. The delay circuitry should insert a certain amount of time delay synchronization pulse based upon the width of the PWM signal. A brief circuit diagram for the PWM is shown in Figure 3. The PWM signal from the SD1200 is a periodical signal with a period that is 511 September, 1998 SmartASIC Confidential 16 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET times of the period of the free-running clock connected to the pin "CLK_1M". System manufacturers may select any frequency for the free running clock. The default clock frequency is 1MHz. System manufacturers also decide the unit delay for the external delay circuitry. The delay information is stored in the EEPROM. When the SD1200 wants to delay the synchronization pulse for N units of delay, it will output the PWM with the high time equal to (N * the period of the free-running clock), and with low time equal to (511-N)* the period of the free-running clock. When N=511, the PWM signal stays high all the time, and when N=0, the PWM signal is always low. Figure 3: SD1200 PWM circuitry block diagram SD1200 PWM Delay Circuitry Ref_Clk PLL Synchronization pulse 3.1.5. Free Running Clock As described in previous section, a free-running clock is needed for the SD1200. This clock is used for many of the SD1200's internal operations. PWM operation is one of them. System manufacturers can select the frequency of the free-running clock, and the default clock frequency is 1MHz. System manufacturer can use an oscillator to generate the free-running clock, and feed that clock directly to the pin "CLK_1M", or use a crystal connecting to "CLK_1M" and "CLK_1M_O". September, 1998 SmartASIC Confidential 17 SmartASIC, Inc. SD1200 3.2. PRELIMINARY DATA SHEET Buffer memory and read/write control block The SD1200 uses internal buffer memory to store a portion of the input image for image scaling and output synchronization. No external memory buffer is needed for the SD1200. The write control logic ensures the input data are stored into the right area of the buffer memory, and the read control logic is responsible to fetch the data from the buffer memory from the correct area and at the correct timing sequence. With the precise timing control of the write and read logic, the output image is appropriately scaled to the full screen, and the output signal is perfectly synchronized with the input signals. 3.3. Image scaling, interpolation and dithering block The SD1200 supports both automatic image scaling and interpolation. 3.3.1. Image scaling The SD1200 supports several different input modes, and the input image may have different sizes. It is essential to support automatic image scaling so that the input image is always displayed to the full screen regardless the input mode. The SD1200 scale the images in both horizontal and vertical directions. It calculates the correct scaling ratio for both directions based upon the LCD panel resolution, and the input mode and timing information produced by the "Input mode detection & auto calibration" block. The scaling ratio is re-adjusted whenever a different input mode is detected. The ratio is then fed to the buffer memory read control logic to fetch the image data with the right sequence and timing. Some of the image data may be read more than once to achieve scaling effect. 3.3.2. Image interpolation The SD1200 supports image interpolation to achieve better image quality. A basic image scaling algorithm replicates the input images to achieve the scaling effect. The replication scheme usually results in a poor image quality. The SD1200 implements both linear interpolation and a proprietary interpolation algorithm. Through external micro-controller, users can chose among different interpolation algorithm. September, 1998 SmartASIC Confidential 18 SmartASIC, Inc. SD1200 3.3.3. Dithering PRELIMINARY DATA SHEET The SD1200 supports 16.7 million true colors for 6-bit panel. Two dithering algorithms are implemented and again users can chose between them through the external micro-controller. 3.4. OSD mixer and LCD interface At the output stage, the SD1200 performs the OSD mixer function, and then generates 24-bit RGB signal to the LCD panel with the correct timing. 3.4.1. OSD mixer In the OSD mixer block, the SD1200 mixes the normal output RGB signal with the OSD signal. The OSD output data is generated based on the "R_OSD", "G_OSD" and "B_OSD" pins as well as the "OSD Intensity" data in EEPROM entry. When the "EN_OSD" is active high, the OSD is active, and the SD1200 will send the OSD data to the LCD panel. The OSD has 16 different color schemes based on the combinations of the three OSD color pins and the "OSD Intensity" data. When R_OSD=1, and OSD_Intensity=0, the SD1200 will output 128 to the output red channel, R_OUT. When R_OSD=1, and OSD_Intensity=1, the SD1200 will output 255. The same scheme is used for G_OSD to G_OUT and for B_OSD to B_OUT. 3.4.2. LCD interface The SD1200 support 48-bit RGB interface with XGA/SXGA LCD panels from various panel manufacturers. The LCD panel resolution and timing information is stored in the external EEPROM. The information in the EEPROM includes timing related to the output back porch, synchronization pulse width and valid data window. The timing information is used to generate the frequency divider for the output PLL, to lock the PLL output clock with HSYNC for the LCD data clock, and to synchronized the output VSYNC and input VSYNC. September, 1998 SmartASIC Confidential 19 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 3.5. EEPROM interface As mentioned in previous sections, the external EEPROM stores much crucial information for the SD1200 internal operations. The SD1200 interfaces with the EEPROM through a 2-wire I2C serial interface. The suggested EEPROM device is an industry standard serial-interface EEPROM (24x08). The I2C interface scheme is briefly described here and detail description can be found in many public literatures. 3.5.1. I2C serial interface The I2C serial interface used 2 wires, SCL and SDA. The SCL is driven by the SD1200, and used mainly as the sampling clock and the SDA is a bi-directional signal and used mainly for data signal. Figure 4 shows the basic bit definitions of I2C serial interface. The I2C serial interface supports random read and sequential read operations. Figure 5 and 6 shows the data sequences for random read and sequential read operations. Figure 4: START, STOP AND DATA Definitions in I2C serial interface DATA START DATA CHANGE STABLE DATA CHANGE STOP September, 1998 SmartASIC Confidential 20 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET Figure 5: Data sequence for single byte random access S T A R T R DEVICE ADDRESS [6:0] E A D A C K WORD ADDRESS [5:0] A C K DATA A C K S T O P M S B LR S /_ BW B I T 0 M S B L S B M S B L S B B I T B I T B I T 0 B I T B I T 0 September, 1998 SmartASIC Confidential 21 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET Figure 6: Data sequence for multiple byte sequential access S T A R T DEVICE ADDRESS [6:0] R E A D A C K WORD ADDRESS [5:0] A C K DATA n A C K DATA n+x S AT CO KP M S B L S B R /_ W M S B M S B L S B M S B L S B B I T B I T 0 B I T B I T B I T 0 B I T B I T 0 6 7 7 7 September, 1998 SmartASIC Confidential 22 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 3.5.2. EEPROM Contents The contents of EEPROM are primarily dependent on the specifications of the LCD panel. SmartASIC provides suggested EEPROM contents for LCD panels from various panel manufacturers. The section presents all the entries in the EEPROM, and briefly describes their definitions. That allows the system manufacturers to have their own EEPROM contents to distinguish their monitors. The EEPROM contents can be partitioned into 11 parts. The first 8 parts are input mode dependent. When the SD1200 detects the input mode, it will then load the information related to the detected mode from the EEPROM. The information in the 9th part is mainly for input mode detection as well as some threshold values for error status indicators. The 10th and 11th parts are look up table for interpolation parameters. The 9th, 10th and 11th parts are loaded in the SD1200 during the reset time. * * * * * * * * * * * Part 1: 640x350 mode, Part 2: 640x400 mode, Part 3: 720x400 mode, Part 4: 640x480 mode, Part 5: 800x600 mode, Part 6: 1024x768 mode, Part 7: 1280x1024 mode, and Part 8: user defined mode Part 9: input mode detection and scaling related parameters Part 10: lookup table for horizontal interpolation Part 11: lookup table for vertical interpolation September, 1998 SmartASIC Confidential 23 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET Part 1-8: Input Mode Dependent Data W 640 x 350 VPW 11 00H 01H VBP 11 02H 03H VBP Source 11 04H 05H Symbol 640 x 400 20H 21H 22H 23H 24H 25H 720 x 400 40H 41H 42H 43H 44H 45H 640 x 480 60H 61H 62H 63H 64H 65H 800 x 600 80H 81H 82H 83H 84H 85H 1024 x 768 A0H A1H A2H A3H A4H A5H 1280 x 1024 C0H C1H C2H C3H C4H C5H INV ALI D E0H E1H E2H E3H E4H E5H Description LCD VSYNC pulse width Target Skip 11 06H 26H 46H 66H 86H Pixel 07H 27H 47H 67H 87H VSIZE HPW HBP HSIZE HTOTAL HTOTAL Source Line Expansion 11 08H 09H 11 0AH 0BH 11 0CH 0DH 11 0EH 0FH 11 10H 11H 12 12H 13H 28H 48H 68H 88H 29H 49H 69H 89H 2AH 4AH 6AH 8AH 2BH 4BH 6BH 8BH 2CH 4CH 6CH 8CH 2DH 4DH 6DH 8DH 2EH 4EH 6EH 8EH 2FH 4FH 6FH 8FH 30H 50H 70H 90H 31H 51H 71H 91H 32H 52H 72H 92H 33H 53H 73H 93H 4 14H 34H 54H 74H 94H [6:3] [6:3] [6:3] [6:3] [6:3] Pixel Expansion 3 14H 34H 54H 74H 94H [2:0] [2:0] [2:0] [2:0] [2:0] LCD VSYNC back porch (including VPW) LCD VSYNC back porch (source equivalent) = VBP * Line Expansion and round up A6H C6H E6H If VBP can not be converted into A7H C7H E7H source evenly, the leftover is converted into number of pixels A8H C8H E8H LCD number of lines A9H C9H E9H AAH CAH EAH LCD HSYNC pulse width ABH CBH EBH ACH CCH ECH LCD HSYNC back porch(including ADH CDH EDH HPW) AEH CEH EEH LCD number of columns AFH CFH EFH B0H D0H F0H LCD total number of pixels per line B1H D1H F1H including all porches B2H D2H F2H LCD total number of clocks per line B3H D3H F3H (source equivalent) = HTOTAL/Line Expansion B4H D4H F4H Vertical source to destination [6:3] [6:3] [6:3] scaling factor 0: 1 to 1 1: 2 to 3 2: 3 to 4 3: 5 to 8 4: 15 to 32 5: 25 to 32 6: 25 to 48 7: 25 to 64 8: 75 to 128 9: 175 to 384 10: 175 to 512 B4H D4H F4H Horizontal source to destination [2:0] [2:0] [2:0] scaling factor 0: 1 to 1 1: 2 to 4 2: 4 to 5 3: 25 to 36 4: 5 to 8 5: 9 to 10 6: 45 to 64 7: 9 to 16 September, 1998 SmartASIC Confidential 24 SmartASIC, Inc. SD1200 Fog Factor 8 15H Horizontal Fog Factor 8 16H 2X Fog Factor 8 17H Vertical Minimum 11 18H input lines 19H PRELIMINARY DATA SHEET 35H 55H 75H 95H B5H D5H F5H Horizontal fogging factor 36H 56H 76H 96H B6H D6H F6H Double of Horizontal fogging factor 37H 57H 77H 97H B7H D7H F7H Vertical fogging factor Maximum 11 input pixels Source HSIZE[11:8] Source VSIZE[11:8] Source HSIZE[7:0] Source VSIZE[7:0] Check sum 3 3 8 38H 58H 78H 98H B8H D8H F8H Minimum input lines = 39H 59H 79H 99H B9H D9H F9H (VSIZE + VBP)* Line Expansion When the input has fewer lines than this value, it is considered as an ERROR, and INPUT_X status bit will be HIGH. 1AH 3AH 5AH 7AH 9AH BAH DAH FAH Maximum input pixels per line. 1BH 3BH 1BH 7BH 9BH BBH DBH FBH Auto clock recovery will not set input PLL divisor larger than this value. 1CH 3CH 5CH 7CH 9CH BCH DCH FCH Source horizontal size upper 3 bits [6:4] [6:4] [6:4] [6:4] [6:4] [6:4] [6:4] [6:4] 1CH 3CH 5CH 7CH 9CH BCH DCH FCH Source vertical size upper 3 bits [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] 1DH 3DH 5DH 7DH 9DH BDH DDH FDH Source horizontal size lower 8 bits 8 1EH 3EH 5EH 7EH 9EH BEH DEH FEH Source vertical size lower 8 bits 8 1FH 3FH 5FH 7FH 9FH BFH DFH FFH Sum of above 31 bytes (keep lower 8 bits only) Part 9: Input Mode Detection Data Symbol Data low threshold Width (bits) 8 Address 120H Description Data high threshold 8 Edge threshold Calibration mode 8 2 Res0 threshold Res1 threshold 10 10 Low water mark for valid data If the data is smaller than this threshold, it is considered LOW internally 121H High water mark for valid data If the data is larger than this threshold, it is considered HIGH internally 122H Minimum difference between the data value of two adjacent pixels to be considered as an edge 123H [1:0] This is to select different operation modes of internal phase calibration. The selection criterion is as follow: 0: when input video signal has large overshot, it results in longest calibration time 1: when input video signal has median overshot, it results in long calibration time 2: when input video signal has normal overshot, it results in normal calibration time (recommended) 3: when input video signal has no overshot, it results in shortest calibration time 124H-125H Upper bound of the line number for 640x350 mode, and lower bound for 640x400 126H-127H Upper bound of the line number for 640x400 mode, September, 1998 SmartASIC Confidential 25 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET and lower bound for 720x400 128H-129H Upper bound of the line number for 720x400 mode, and lower bound for 640x480 12AH-12BH Upper bound of the line number for 640x480 mode, and lower bound for 800x600 12CH-12DH Upper bound of the line number for 800x600 mode, and lower bound for 1024x768 12EH-12FH Upper bound of the line number for 1024x768 mode, and lower bound for 1280x1024 130H-131H Upper bound of the line number for 1280x1024 mode. If the input has more line than this threshold, it is considered INVALID mode 132H[1:0] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 132H[3:2] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 132H[5:4] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 132H[7:6] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 133H[1:0] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 133H[3:2] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 133H[5:4] The polarity of input synchronization signals Bit 0 is for VSYNC and bit 1 is for HSYNC 134H The maximum vertical back porch for input video 135H-136H The unit delay used in the external PWM delay circuitry. If the free-running clock is 1MHz, and the intended unit delay is 0.2 ns (= 5,000MHz), then a value of 5,000MHz/1MHz = 5,000 is used here. 137H-139H Maximum time when input VSYNC is off before the LINK_DWN pin turns ON (unit: clock period of the free running clock). If the free-running clock is 1MHz, and the intended maximum time is 1 second, then a value of 1,000,000 us/ 1 us = 1,000,000 is used here. 13AH-13BH Maximum refresh rate supported by the LCD panel If the intended maximum refresh rate is 75Hz, and the free-running clock is 1MHz, then a value of 1000000/75=133,333 is used here 13CH Maximum source clock rate supported by the SD1200 (unit: frequency of free-running clock) If the intended maximum clock rate is 60MHz, and the free-running clock is 1MHz, then a value of 60 is used here. If the input signal has a higher frequency than this value, the VCLK0_X status bit will turn ON. 13DH Scale factor used when generate look up table for current even pixel multiplication 13EH Scale factor used when generate look up table for current odd pixel multiplication 13FH Scale factor used when generate look up table for next even pixel multiplication Res2 threshold Res3 threshold Res4 threshold Res5 threshold Res6 threshold 10 10 10 10 10 Mode 640x350 Sync Polarity Mode 640x400 Sync Polarity Mode 720x400 Sync Polarity Mode 640x480 Sync Polarity Mode 800x600 Sync Polarity Mode 1024x768 Sync Polarity Mode 1280x1024 Sync Polarity Maximum VBP PWM unit delay 2 2 2 2 2 2 2 8 13 Maximum link off time 22 Maximum refresh rate 16 Maximum input frequency 8 Scale factor CE Scale factor CO Scale factor NE 8 8 8 September, 1998 SmartASIC Confidential 26 SmartASIC, Inc. SD1200 Scale factor NO Offset factor CE Offset factor CO Offset factor NE Offset factor NO Scale factor V Offset factor V Minimum pixels per line for LCD LCD polarity 8 8 8 8 8 8 8 11 4 140H PRELIMINARY DATA SHEET Scale factor used when generate look up table for next odd pixel multiplication 141H Offset factor used when generate look up table for current even pixel multiplication 142H Offset factor used when generate look up table for current odd pixel multiplication 143H Offset factor used when generate look up table for next even pixel multiplication 144H Offset factor used when generate look up table for next odd pixel multiplication 145H Scale factor used when generate look up table for line multiplication 146H Offset factor used when generate look up table for line multiplication 147H-148H Minimum number of pixels per line for LCD panel 149H[3:0] Controls the polarity of output VSYNC, HSYNC, clock and display enable Bit0: 0: clock active high, 1: clock active low Bit1: 0: HSYNC active low, 1: HSYNC active high Bit2: 0: VSYNC active low, 1: VSYNC active high Bit4: 0: de active high, 1: de active low Sum of all part 9 bytes (keep only lower 8 bit) Check sum 8 14AH Part 10: Horizontal Interpolation Lookup Table Symbol Mapped value Width (bits) 8 Address Description Check Sum 8 1C0H-2BFH This is the base table for all four horizontal interpolation lookup tables. Each table is then generated by multiply this value with corresponding scale factor and added with corresponding offset factor. 2C0H Sum of all part 10 entry (only keep lower 8 bits) Part 11: Vertical Interpolation Lookup Table Symbol Mapped value Width (bits) 8 Address Description Check Sum 8 2E0H-3DFH This is the base table for vertical interpolation lookup table. The vertical interpolation table is then generated by multiply this value with vertical scale factor and added with vertical offset factor. 3E0H Sum of all part 10 entry (only keep lower 8 bits) September, 1998 SmartASIC Confidential 27 SmartASIC, Inc. SD1200 3.6. CPU interface PRELIMINARY DATA SHEET The SD1200 supports 2-wire I2C serial interface to external CPU. The interface allows external CPU to access and modify control registers inside the SD1200. The I2C serial interface is similar to the EEPROM interface, and the CPU is the host that drives the SCL all the time as the clock and for "start" and "stop" bits. The SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. This interface supports random and sequential write operations for CPU to modify one or multiple control registers, and random and sequential read operations for CPU to read all or part of the control registers. The lower 4 bits of device ID for SD1200 are fixed at "1010". The upper 3 bits are programmable through MODE_IN3 (pin 19), MODE_IN2 (pin 18) and MODE_IN1 (pin 15). This avoids any conflict with other I2C devices on the same bus. The following table briefly describes the SD1200 control registers. External CPU can read these register to know the state of the SD1200 as well as the result of input mode detection and phase calibration. External CPU can modify these control registers to disable several SD1200 features and force the SD1200 into a particular state. When the CPU modifies the control registers, the new data will be first stored in a set of shadow registers, and then are copied into the actual control registers when the "CPU Control Enable" bit is set. When the "CPU Control Enable" bit is set, the external CPU will retain control and the SD1200 will not perform the auto mode detection and auto calibration. The external CPU is able to adjust the size of the output image and move the output image up and down by simply changing the porch size and pixel and line numbers of the input signal. These adjustments can be tied to the external user control button on the monitor. A set of four control registers are used to generate output signal when there is no input signal available to the SD1200, or the input signal is beyond the acceptable ranges. This operation mode is called standalone mode, which is very important for the end users when they accidentally select an input mode beyond the acceptable range of the SD1200, or when the input cable connection becomes loose for any reason. System September, 1998 SmartASIC Confidential 28 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET manufacturers can display appropriate OSD warning messages on the LCD panel to notify the users about the problem. Table 3: SD1200 Control Registers Symbol VBP Source VSIZE Source VTOTAL Source HBP Source HSIZE Source HTOTAL Source Mode Source Width Mode 11 RW 11 11 11 11 11 3 RW RW RW RW RW RW Clock Phase Source VPW standalone VTOTAL standalone HPW standalone HTOTAL standalone Disable auto calibration for mode 640x350 Delay auto calibration for mode 640x350 Disable auto calibration for mode 640x400 Delay auto calibration for mode 640x400 Disable auto calibration for mode 720x400 Delay auto calibration for mode 720x400 Disable auto calibration for mode 640x480 Delay auto calibration for mode 640x480 9 10 10 10 10 1 RW RW RW RW RW RW 15 1 RW RW 15 1 RW RW 15 1 RW RW 15 RW Address Description 0H-1H Input VSYNC back porch (not include pulse width) 2H-3H Input image lines per frame 4H-5H Input total number of lines including porches 6H-7H Input HSYNC back porch (not include pulse width) 8H-9H Input image pixels per line AH-BH Input total number of pixels per line including porches CH[2:0] Input video format 0: 640x350 1: 640x400 2: 720x400 3: 640x480 4: 800x600 5: 1024x768 6: 1280x1024 7: invalid DH-EH Input sampling clock phase FH-10H For standalone mode, the pulse width of VSYNC 11H-12H For standalone mode, total number of line per frame 13H-14H For standalone mode, HSYNC active time in us 15H-16H For standalone mode, HSYNC cycle time in us 17H[7] Disable auto calibration for this mode 1: disable 0: enable 17H[6:0]- The number of frames need to be skipped before 18H starting auto calibration for this mode 19H[7] Disable auto calibration for this mode 1: disable 0: enable 19H[6:0]- The number of frames need to be skipped before 1AH starting auto calibration for this mode 1BH[7] Disable auto calibration for this mode 1: disable 0: enable 1BH[6:0]- The number of frames need to be skipped before 1CH starting auto calibration for this mode 1DH[7] Disable auto calibration for this mode 1: disable 0: enable 1DH[6:0]- The number of frames need to be skipped before 1EH starting auto calibration for this mode September, 1998 SmartASIC Confidential 29 SmartASIC, Inc. SD1200 Disable auto calibration for mode 800x600 Delay auto calibration for mode 800x600 Disable auto calibration for mode 1024x768 Delay auto calibration for mode 1024x768 Disable auto calibration for mode 1280x1024 Delay auto calibration for mode 1280x1024 Disable auto calibration for mode INVALID Delay auto calibration for mode INVALID Bypass Sync Polarity 1 RW 1FH[7] PRELIMINARY DATA SHEET Disable auto calibration for this mode 1: disable 0: enable The number of frames need to be skipped before starting auto calibration for this mode Disable auto calibration for this mode 1: disable 0: enable The number of frames need to be skipped before starting auto calibration for this mode Disable auto calibration for this mode 1: disable 0: enable The number of frames need to be skipped before starting auto calibration for this mode Disable auto calibration for this mode 1: disable 0: enable The number of frames need to be skipped before starting auto calibration for this mode Bypass Input SYNC polarity detection (default 0) 1: bypass input SYNC polarity detection 0: detect input SYNC polarity and make them negative polarity Enable SYNC polarity check during input mode detection (default all 0). 1: enable SYNC polarity based mode detection 0: disable SYNC polarity based mode detection bit 0: 640x350 bit 1: 640x400 bit 2: 720x400 bit 3: 640x480 bit 4: 800x600 bit 5: 1024x768 bit 6: 1280x1024 Enable dithering for 6 bit panel (default 0) 1: enable dithering 0: disable dithering Enable frame modulation for 6 bit panel (default 0) 1: enable frame modulation 0: disable frame modulation Enable horizontal interpolation (default 0) 1: enable horizontal interpolation 0: disable horizontal interpolation Enable vertical interpolation (default 0) 1: enable vertical interpolation 0: disable vertical interpolation Enable horizontal rounding (default 0) 1: enable horizontal rounding 0: disable horizontal rounding Enable vertical rounding (default 0) 1: enable vertical rounding 0: disable vertical rounding Enable horizontal Table Lookup (default 0) 15 1 RW RW 1FH[6:0]20H 21H[7] 15 1 RW RW 21H[6:0]22H 23H[7] 15 1 RW RW 23H[6:0]24H 25H[7] 15 1 RW RW 25[6:0]26H 27H[7] Enable SYNC Check 7 RW 27H[6:0] Dithering Enable 1 RW 28H[7] Frame Modulation Enable 1 RW 28H[6] Horizontal Interpolation Enable Vertical Interpolation Enable Horizontal Rounding Enable Vertical Rounding Enable Horizontal Table 1 RW 28H[5] 1 RW 28H[4] 1 RW 28H[3] 1 RW 28H[2] 1 RW 28H[1] September, 1998 SmartASIC Confidential 30 SmartASIC, Inc. SD1200 Lookup Enable Vertical Table Lookup Enable HSYNC Threshold Enable 1 RW PRELIMINARY DATA SHEET 1: enable horizontal Table Lookup 0: disable horizontal Table Lookup 28H[0] Enable vertical Table Lookup (default 0) 1: enable vertical Table Lookup 0: disable vertical Table Lookup 29H[4] Enable detection of short lines (IBM panel only, default 0) 1: Enable such detection 0: disable such detection 29H[3] OSD intensity selection 0: half intensity 1: full intensity 29H[2] Should be kept low most time. A high pulse will force SD1200 to reload all EEPROM entries 29H[1] Should be kept low most time. A high pulse will force SD1200 to reload mode dependent EEPROM entries 29H[0] External CPU control enable 0: disable external CPU control. SD1200 can write control registers, but CPU only read control registers. 1: enable external CPU control. CPU can read/write control registers. SD1200 cannot write control registers 2AH Read only internal status registers 1: indicate error status 0: indicate normal status Bit 0: EEPROM vertical lookup table loading Bit 1: EERPOM horizontal lookup table loading Bit 2: EEPROM mode dependent entries loading Bit 3: EEPROM calibration entries loading Bit 4: input has too few lines Bit 5: no input video Bit 6: input data clock is too fast Bit 7: refresh rate exceed LCD panel specification 2BH[3:0] Internal auto calibration state 1 RW OSD Intensity 1 RW Load ALL EEPROM Load Mode Dependent EEPROM CPU control enable 1 1 RW RW 1 RW Status 0 8 R Status 1 4 R September, 1998 SmartASIC Confidential 31 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 4. ELECTRICAL SPECIFICATION This section presents the electrical specifications of the SD1200. 4.1. Symbol VCC VIN VOUT TSTG Absolute Maximum Ratings Parameter Power Supply Input Voltage Output Voltage Storage Temperature Rating -0.3 to 6.0 -0.3 to VCC + 0.3 -0.3 to VCC +0.3 -55 to 150 Units V V V C 4.2. Symbol VCC VCC VIN TJ TJ Recommended Operating Conditions Parameter Commercial Power Supply Industrial Power Supply Input Voltage Commercial Junction Operating Temperature Industrial Junction Operating Temperature Min. 4.75 4.5 0 0 -40 Typ. 5.0 5.0 25 25 Max. 5.25 5.5 VCC 115 125 Units V V V C C 4.3. Symbol IIL IOZ CIN COUT CBID3 General DC Characteristics Parameter Input Leakage Current TRI-state Leakage Current Input Capacitance Output capacitance Bi-directional buffer capacitance Conditions no pull - up or pull - down Min. -1 -10 3 3 3 Typ. Max. 1 10 Units A A F F F Note: The capacitance above does not include PAD capacitance and package capacitance. One can estimate pin capacitance by adding pad capacitance, which is about 0.5 F and the package capacitance September, 1998 SmartASIC Confidential 32 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 4.4. Symbol VIL VIH VT- DC Electrical Characteristics for 3.3 V Operation Parameter Input low voltage Input high Voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up /down resistance Conditions CMOS CMOS COMS Min. 0.7*VCC 1.22 Typ. Max. 0.3*VCC Units V V V (Under Recommended Operation Conditions and VCC = 3.0 ~ 3.6V, TJ = 0C to +115C) VT+ COMS 2.08 V VOL VOH RI IOH=2,4,8,12, 16,24 mA IOH=2,4,8,12, 16,24 mA VIL=0V or VIH=VCC 0.4 2.4 75 V V K 4.5. Symbol VIL VIH VIL VIH VTVT+ DC Electrical Characteristics for 5V Operation Parameter Input low voltage Input high voltage Input low voltage Input high voltage Schmitt trigger negative going threshold voltage Schmitt trigger Positive going threshold voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up / down resistance Conditions COMS COMS TTL TTL CMOS COMS Min. 0.7*VCC 0.8 2.0 1.84 3.22 Typ. Max. 0.3*VCC Units V V V V V V (Under Recommended Operation Conditions and VCC=4.75~5.25,TJ=0C to +115C) VTVT+ TTL TTL 1.10 1.87 V V VOL VOH RI IOL=2,4,8,16,24mA IOH=2,4,8,16,24 mA VIL=0V or VIH=VCC 0.4 3.5 50 V V K September, 1998 SmartASIC Confidential 33 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 5. PACKAGE DIMENSIONS September, 1998 SmartASIC Confidential 34 SmartASIC, Inc. SD1200 PRELIMINARY DATA SHEET 6. ORDER INFORMATION Order Code SD1200 Temperature Commercial 0C ~ 70C Package 160-pin PQFP 14 x 20 (mm) Speed 60MHz SmartASIC, Inc. WORLDWIDE OFFICE U.S.A. (Headquarter) 2674 N. First Street, Suite 112 San Jose, CA 95134 U.S.A. Tel : 1-408-383-1818 Fax : 1-408-383-1819 Asia Pacific 13F, No. 11, Chung-Shan N. RD. Taipei, Taiwan R.O.C. Tel : 886-2-2542-5169 Fax : 886-2-2542-5166 @Copyright 1998, SmartASIC, Inc. This information in this document is subject to change without notice. SmartASIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. SmartASIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. September, 1998 SmartASIC Confidential 35 |
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